Labs:

Lab 1. VHDL - Combinatorial circuits.
Lab 2. VHDL - Arithmetic circuits.
Lab 3. VHDL - Latch and D flip-flop.
Lab 4. VHDL - Sequential circuits.
Lab 5. VHDL - Finite state machines.
Lab 6. Alliance - Environment.
Lab 7. Alliance - Adder design.
Lab 8. Alliance - Finite state machine design.
Lab 9. Alliance - Pad ring place and route.
Lab 10. Final examination of project.

Design Project: Semi-custom ASIC Design using Alliance: Multiplier (romanian)

Week 1/2 : Lesson 1 - Project theme
Week 3/4 : Lesson 2 - Spec description. Multiplier design example
Week 5/6 : Lesson 3 - Alliance conversion using vasy
Week 7/8 : Lesson 4 - Pad ring, place and route. Multiplier design example.
Week 9/10 : Lesson 5 - Final examination of project

 

Links:

VHDL Reference Manual
Alliance Home Page - VLSI CAD system