This thesis looks at the integrated circuits (IC) test domain mainly from the electronic device users point of view. The proposed testing systems are analysed and practical models are implemented using an university electronics laboratory equipment.
Since the thesis presents the realisations of an engineer specialised in electronic circuits design and implementation that's why some practical realised testing systems, employing a number of original circuits and computer programs, were presented, without focusing on the modernity or actuality of the adopted solutions nor on some very high level theoretical studies.
The work consists of two parts and is organised in 7 chapters. The first part, the first two chapters, give a general presentation of the testing domain and presents some particularities of using the personal computer (PC) as a part of the testing system. In the second part of this work the author research efforts in the testing domain were presented and some original testing systems were proposed for the parametrical, functional and structural testing methods.
The parametrical testing system automatically plots the input and transconductance static characteristics for a very large current domain that flows via the tested bipolar transistor. The practical implemented system is based on a data acquisition module and the computer programs for control, measure and data display were written in LabVIEW environment.
The functional testing system determinates the linearity and gain error for the digital to analog (D/A) converter. Two different approaches were compared: a PC with data acquisition module with a LabVIEW software (with a simpler interface between the acquisition module and the converter) and a more complex interface controlled from the PC standard parallel port (SPP).
The most important part of the thesis consists of the integrated circuits structural testing system using terminal characteristics analysis. The basis of the testing method is the IC terminal characteristics plotting, by measuring few voltage/current pairs for any of the IC terminal pair. The proposed method can test a lot of different types of IC: digital, analog or mixed signal IC, made with different technologies: bipolar, CMOS or BiCMOS. This testing method can be used for the IC suspected to be damaged because of an electrical shock that generally produce a different behaviour of the IC at the terminals where the shock appeared. The testing system block diagram, some of the circuits schematics with some of theirs design formulae, some data structures and programs are presented. A maximum 16 pins DIL IC testing system was conceived and realised.
The main circuits of this system are:
The control circuit made the connection between the digital interface and PC SPP. The signal conditioning circuit defines a two domains measurement procedure in order to achieve a better precision (especially for the little voltages). The analog validation block finds out the moment when the transitory period ends and starts the acquisition.
The command data and measured data organisation was presented. Two different methods for data analysis (in order to get the voltage limits) were proposed:
- an empirical method that defines the so named "connection types" based on the internal structure IC analysis and some experimental data sets analysis,
- a statistical method based on a great number of good IC analyses.
The testing co-ordination and data processing software was implemented in DELPHI language. The key of the empirical method is the optimum definition of the connection types. The IC are insufficiently tested if the voltage limits are too tight or too wide or if not all the necessary connection types are defined. More than 300 IC-s (more than 30 different types, digital and analog), were tested using the structural testing method and most of the practical problems with the testing system were solved. The transitory period is between 20 ms and 0.55 ms; the usual values are between 70…100 ms and some times (special situations only) the delay is greater than 1ms. The average length of a complete measurement (which include the acquisition made for verification) can be estimated between 0,25…0.35 ms with the limits between 0.15…7 ms. The flexibility of the analog signal validation circuit and the testing algorithm structure, assure a good precision of the system, with a supplementary delay of about 0.1ms for every measurement.
Comparing this method with the classical ones, one can see the main advantage is the simplicity and coming with this: the reduced cost, high testing speed and the testing system portability. The second advantage is that most of the IC-s types can be tested using this method. The main disadvantage is the uncertain positive answer of that method and some supplementary test method (some functional tests for example) must be used, but this disadvantage is specific to most of the structural testing methods.
The main contributions of the author in this thesis are:
- creation and implementation of the IC structural testing method using terminal characteristics;
- creation the architecture of a wide range current generator with a precision better than 1%;
- creation the architecture of the IC structural testing system using terminal characteristics;
- creation the architecture of the circuit which determinates the linearity and gain error of D/A by comparing the current D/A converter (tested) with a voltage D/A converter (reference);
- conception of a gain error compensation circuit for the D/A converter tested by the comparing test method;
- conception, optimisation and implementation of an analog signal validation circuit which automatically determinates the moment the transitory operation mode of a signal ends, if the slew rate of that signal is over a certain value;
- conceive and implementation of a dynamically logical level circuits converter from TTL to high voltage CMOS level for a binary signals group which has to be memorised in latches;
- implementation of a virtual instrument (VI) that automatically plots the statically characteristics of the bipolar transistor, with a data acquisition module, for a wide range of current that flow via the transistor;
- implementation of a virtual instrument (VI) that automatically calculates the linearity and gain error for an 8 bits D/A converter;
- definition and optimisation of a PC SPP protocol by: signal assign, definition of the control and data measurement algorithms and procedures, used for IC structural testing;
- study of the software and hardware timings in order to realise a real time computer system;
- implementation of a software timing control for microseconds delays, by calibrating the program loops with an external signal that gave processor clock independent delay;
- defining the databases structures that allow the system to be developed to a maximum of 128 pins for the IC under test;
- creation of the algorithms and the program specifications for the co-ordinator program written in DELPHI environment, for the structural testing of IC using the empirical method;
- implementation (in assembly language) of an interactive control and data processing, memorisation and display program for the IC structural testing;
- conception of the data structures, which is the basis of the statistical analysis methods that generates the test vector using the databases.
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