LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY mux_2x1_tb IS
PORT ( i1  : OUT std_logic;
       i0  : OUT std_logic;
       sel : OUT std_logic);
END mux_2x1_tb;  

ARCHITECTURE mux_2x1_tb OF mux_2x1_tb IS
BEGIN
  i1 <= '0', '1' AFTER 10 ns, '0' AFTER 30 ns, '1' AFTER 80 ns,
             '0' AFTER 110 ns;
  i0 <= '1', '0' AFTER 40 ns, '1' AFTER 60 ns, '0' AFTER 70 ns,
             '1' AFTER 90 ns;
  sel <= '1', '0' AFTER 20 ns, '1' AFTER 50 ns, '0' AFTER 85 ns;	     
END mux_2x1_tb;