LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY mux_2x1_comp IS
PORT ( i1	: IN  std_logic;
       i0	: IN  std_logic;
       sel	: IN  std_logic;	
       o_beh    : IN  std_logic;
       o_df     : IN  std_logic;
       o_guard  : IN  std_logic;
       error    : OUT std_logic);
END mux_2x1_comp;  

ARCHITECTURE mux_2x1_comp OF mux_2x1_comp IS
BEGIN
  P2: PROCESS( i1, i0, sel ) 
  BEGIN
    IF ((o_beh = o_df) AND (o_beh = o_guard)) THEN
      error <= '0';
    ELSE
      error <= '1';
    END IF;
  END PROCESS P2;
END mux_2x1_comp;