SCMAP

NAME

scmap

- mapping of a behavioural description onto a standard cell library.

 

ORIGIN

SYNOPSIS

scmap data_flow_file output_file [parameter_file]

DESCRIPTION

Input description

The logic level behavioural description (.vbe file) uses the same VHDL subset as the logic simulator asimut, the FSM synthesizer syf, the functional abstractor yagle and the formal prover proof (for further information about the subset of VHDL, see the "vbe" manual).
A special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs and internal registers : A bit signal can take the 'd' value. This value is interpreted as a '0' by the logic simulator asimut. Don't Cares are automatically generated by syf in the resulting '.vbe' file.
For the register signal, only one signal can appear in a guarded expression since the STABLE attribute is used. This attribute is only supported by technology mapping onto a standard cell library as sclib.

scmap is the second step of the logic synthesis : it builds a gate network using
 a predefined standard cell library as SCLIB. 

Mapping with a standard cell library

Every cell appearing in the directory defined by the environment variable MBK_TARGET_LIB may be used by scmap since they are described as a '.vbe' file. There are some restrictions about the type of the cell used. Every cell has to have only one output. For the combinational cells, two levels maximum (AND-OR or OR-AND) are required for the logical function. The cell must be characterized. The timing and area informations required by scmap are specified in the "generic" clause of the ".vbe" file.

Parameter file '.lax'
The parameter file is common with other logic synthesis tools and is used for driving the synthesis process. lax uses a lot of parameters to guide every step of the synthesis process. Some parameters are globally used (for example, optimization level whereas others are specifically used (load capacitance for the netlist optimization only). Here is the default parameter file (see the user's manual for further information about the syntax of the '.lax' file):

   Optimization mode = 2 (50% area - 50% delay)

   Optimization level = 2 

   Delayed input = 0

   Early output = 0

   Auxiliary signal saved = 0

   Number of serial transistors = 4 in N and P area

ENVIRONMENT VARIABLES

        MBK_WORK_LIB gives the path of the directory of both input and output files (behavioural, structural and parameters description).

        MBK_CATA_LIB gives the auxiliary paths of the directories of input files (behavioural description).

        MBK_TARGET_LIB gives the path (single) of the directory of the selected standard cell library.

        MBK_C4_LIB gives the path (single) of the directory for the three views of each cell generated by C4.

        MBK_IN_LO gives the format of models instantiated in the structural description.

        MBK_OUT_LO gives the output format of the structural description.

        MBK_OUT_PH gives the output format for the layout of the cells generated by C4.

EXAMPLE