This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at ASIM/LIP6/UPMC laboratory.
E-mail support : alliance-support@asim.lip6.fr
Made to run on a data-flow description, proof supports the same subset of VHDL as asimut and bop and scmap (for further informations about this subset, please call the VHDL manual). proof uses a Reduced Ordered Binary Decision Diagrams representation that permits the designer to prove easily the functionnal equivalence between two behavioral descriptions. proof is generally used in order to compare a behavioural specification with an extracted behaviour obtained by yagle.
In default mode, a collapsing phase is done on the description by removing all the auxiliary signals (the BDD of the outputs, the registers and the buses are described from the inputs or the registers). The two descriptions must contain the same ressources (signals register with the same name). It is possible to use the .inf file in yagle to rename the registers in the extracted behavioural description (see man yagle). The datas and the commands (the guarded expressions) must match separatly. The buses corresponding to completely specified logical functions are represented by a logical multiplexor in both descriptions. The two descriptions must have the same interface (VHDL entity), if they do not, the formal proof is stopped.
proof only uses two system environment variables related to the work directory.
proof -a -d adder1 adder2
This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi research team.
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If you find bugs, please fill-in the form at
http://www-asim.lip6.fr/alliance/support/bug-report/
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This document was created by
man2html, using the manual pages.