M. Cirstea,
A. Dinu,
D. Nicula
Editura Tehnica, Bucharest, Romania
ISBN: 973-31-1539-8
Preface |
Table of Contents
The idea of writing this book has arisen from the need to teach the main
features / principles of VHDL design to advanced digital electronics
students in a very short time and based on a practical approach. This
primarily attempts to form design skills using VHDL rather than to provide
an in-depth theoretical description of the language. Therefore, the book
mainly aims to be a quick learning guide / user guide for students/beginners
interested to learn VHDL design. In the same time, it is structured in a
manner that addresses more complex needs of professional designers using
VHDL by including a series of comprehensive design examples. It facilitates
the understanding of hardware description language basics and it provides a
practical, example-based approach to learning VHDL design.
There is a large number of design engineers who prefer to develop a design
module and/or learn another design method - in this case the VHDL language -
by following given examples rather than reading a lot of descriptive theory.
The first section of the book contains a description of the VHDL language,
briefly covering most of the main aspects, which will allow a beginner
student to understand the essence of this HDL and will also serve to a VHDL
designer as a review / quick guide of the language. The second section
contains complete examples of common digital electronic design modules. They
can be used by students as a quick guide to start writing VHDL code, and by
experienced designers as "core" elements for developing complex digital
systems. Most of the examples presented can be used as such. Thanks are due
to all students who helped in testing the VHDL files used as examples.
However, in order to complete the design of advanced digital systems and/or
for a deeper understanding of the very complex features of VHDL, extra
reading is strongly recommended and some well structured and comprehensive
material is listed in the Bibliographical section of the book. The titles
mentioned cover in details most of the VHDL theoretical aspects, and include
complete examples. The main positive difference offered by this book is that
it will be a quick and short guide through the complex matters of VHDL
design rather than a prolix approach of the topic. In the same time it gives
complex models / examples of VHDL synthesisable code, which can be used by
both beginner students or experienced designers. The cost of the book will
hopefully make it affordable to a large number of students.
The authors.
- VHDL FUNDAMENTALS
- Introduction
- Top-Down Design Methodology Approach
- Definition of Terms
- Behavioural & Structural Design
- VHDL Design Units
- Design Unit Names
- Entity
- Architecture
- Configuration
- Package
- Package Body
- Libraries, Visibility and State System in VHDL
- Libraries
- Visibility
- State System
- VHDL Simulation
- Sequencial Statements
- Process
- Wait
- If-Then-Else
- Case
- Loop
- Assert
- Concurrent Statements
- Assert
- Component Instantiation
- Generate
- Signal Assignment
- Functions and Procedures
- Functions
- Function Body
- Procedures
- Procedure Body
- Advanced Features in VHDL
- Attributes
- Overloading
- Passive Processes
- TEXTIO
- Summary
- VHDL DESIGN EXAMPLES
- Introductory Example
- Behavioural Multiply_Accumulate Device
- Structural Multiply_Accumulate Device
- And-or-invert
- Basic Digital Electronic Modules
- Adders
- Subtracters
- Registers
- Multipliers
- Counters
- More Complex Modules - Memory Devices
- Data types for memory devices
- Memory model initialisation
- ROM
- RAM
- PAL
- Complex Design Examples
- Adjustable Speed-Complexity Ratio Digital Multiplier
- Variable Frequency Sinewave Generator
- VHDL CASE STUDY
- Design Specifications
- The Design Process
- Control Unit
- Counters
- Decoding
- Downloading
- VHDL DESIGN FOR SYNTHESIS
- Synchronous Circuits
- Clock Buffering
- Not-recommended
- Recommended
- Gated Clock
- Not-recommended
- Recommended
- Double-edge Clocking
- Not-recommended
- Recommended
- Asynchronous Reset
- Not-recommended
- Recommended
- Not-recommended
- Recommended
- Shift Registers
- Not-recommended
- Recommended
- Asynchronous Inputs
- Delay Lines and Monostables
- Not-recommended
- Recommended
- Modelling Combinatorial Logic
- General Recommendations
- Modelling logic gates
- Modelling multiplexers using 'case' or 'if' statements
- Modelling arithmetic circuits
- Modelling complex combinatorial logic
- Modelling Sequential Logic Circuits
- General recommendations
- Modelling synchronous systems
- Modelling clock signal
- Modelling FSM implicitly
- Modelling FSMs explicitly
- Modelling the Reset Signal
- Power-up reset
- Asynchronous reset
- Synchronous reset
- Using an enable signal instead of a gated clock
- BIBLIOGRAPHY
- AUTHOR BIOGRAPHIES